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TMC2072
Genlocking Video Digitizer
Features
* * * * * * * * * * * Fully integrated acquisition 3-channel video input multiplexer Two-stage (analog and digital) video clamp Automatic gain adjustment Sync detection and separation Pixel and subpixel adjustment of video-to-sync output timing Genlock to any NTSC or PAL format, including PAL-M and PAL-N Pixel clock generation 8-bit video A/D conversion Standard R-bus serial microprocessor interface User-selectable line-locked pixel rates include: - 12.27 MHz NTSC & PAL-M - 13.5 MHz NTSC & all PAL - 14.75 MHz PAL (non-M) TMC2072-1 only - 15.0 MHz PAL (non-M) TMC2072-1 only Direct interface to Fairchild Semiconductor video encoders and decoders Built-in circuitry for crystal oscillator No tuning or external voltage reference required Space-saving 100-lead MQFP package
Description
The TMC2072 Genlocking Video Digitizer samples and quantizes standard analog baseband composite NTSC or PAL video into its 8-bit digital equivalent. It extracts horizontal and vertical sync signals, from which an on-chip PLL generates a line-locked pixel clock for the on-chip 8-bit A/D converter and a double-speed register clock to transfer data to a subsequent video processing subsystem. A second PLL generates a chroma subcarrier locked to the incoming chroma burst. The chip reports each line's color burst phase and frequency during the next horizontal sync pulse. The TMC2072 includes a three-channel video input multiplexer, analog clamp, variable gain amplifier, and digital back porch clamp. The user may provide either an external 20MHz clock or a 20MHz crystal. No external component changes or tuning are required for PAL or NTSC operation at either D1 or square pixel VGA pixel rates. The TMC2072 is fabricated in a submicron CMOS process and is packaged in a 100-lead MQFP. Its performance is guaranteed from 0 to 70C.
* * * *
Applications
* Frame grabber * Digital videotape recorders * Desktop video
Block Diagram
BACK PORCH CLAMP VIN1 DATA SELECTOR CVBS7-0
MUX
VIN2 VIN3
ANALOG CLAMP
GAIN
A/D
SUBCARRIER PHASE-LOCKED LOOP LOWPASS FILTER
D/A
SYNC SEPARATOR
GVSYNC GHSYNC
D/A CONTROL +1.2V DIRECT DIGITAL SYNTHESIZER HORIZONTAL PHASE-LOCKED LOOP PXCK LDV VALID
PFD IN
EXT PXCK
CLK IN
PXCK SEL
SCL SA2-0
RESET SDA
COMP VREF
INT
CLK OUT
DDS OUT
RT
CBYP
RB
65-2072-01
MICROPROCESSOR INTERFACE
ANALOG INTERFACE
DDS/PIXEL CLOCK INTERFACE
REV. 1.0.4 6/19/01
TMC2072
PRODUCT SPECIFICATION
Functional Description
The TMC2072, a fully integrated self-genlocking video A/D converter, digitizes NTSC or PAL baseband composite signals. It accepts video on one of three input channels, adjusts the gain, clamps to the back porch and digitizes the video at a user-selectable multiple of the horizontal line frequency. It extracts horizontal and vertical sync, measures the subcarrier frequency and phase, and provides these data with the digitized composite data over an 8-bit digital video port. Horizontal and vertical sync outputs are provided, along with pixel clock (LDV) and twice pixel clock (PXCK). Operating parameters are set up via a standard two-wire microprocessor port. The chip can work with either an internal or an external voltage reference. Fabricated in an advanced CMOS process, the TMC2072 is housed in a 100 lead metric quad flat package. Its performance is guaranteed from 0 to 70C and from 4.75 to 5.25 supply volts.
engages for one video frame following either: 1) initial lock after reset; 2) loss and recovery of lock while operating; or 3) setting of control bit AGCEN high by the host microprocessor. The AGC operation adjusts the A/D converter's onchip reference voltages until video blank causes it to output approximately 1/4 of its full range. The chip then holds this gain adjustment constant until a new AGC sequence is initiated by AGCEN going high or by loss and recovery of video lock. The one-frame timeout prevents the gain control from riding gain and trying to track noise or minor variations in signal strength. To handle doubly-terminated and other weak video signals, the user should set the VGAIN control bit high, thereby boosting video gain 50% above nominal.
Analog-to-Digital Converter
The TMC2072 contains a high-performance 8-bit A/D converter. Its gain and offset are automatically set as a part of the automatic gain adjustment process during initial signal acquisition, and require no user attention. The reference voltages to the A/D converter are set up by internal D/A converters under automatic control during genlock acquisition. These voltages determine the gain and offset of the A/D converter with respect to the video level presented at its input.
Timing
The TMC2072's A/D converter and digital signal path operate from alternate cycles of an internally-synthesized clock, PXCK. This 24.5 to 30 MHz clock is derived from the incoming 20 MHz reference clock and phase-locked to the horizontal sync tips of the incoming analog video stream. The frequency of PXCK may be set as 1560 (NTSC VGA square pixel), 1716 (NTSC D1), 1732 (PAL D1), or 1888 or 1920 (PAL VGA) times the incoming video line rate. Timing of the serial microprocessor interface bus is independent of the pixel clock and is described under the Microprocessor Interface section that follows Functional Description.
Low-Pass Filter
The digitized composite video stream is digitally low-pass filtered to remove chrominance components from the sync separator. Filtering provides robust operation by optimizing the signal-to-noise ratio of the synchronizing/blanking portion of the video, improving the accuracy of the back porch blanking level detector. A digital sync separator provides the output sync signals, GHSYNC and GVSYNC, and times internal operations.
Video Input
Via the microprocessor interface, the user can enable one of the chip's three analog video input ports. Although each port normally anticipates a standard video signal level with 286 to 300 mV between sync tip and blank, another control register bit allows it to be used with half-power (approximately 70% amplitude) signals. Good crosstalk isolation accommodates active video on all three inputs simultaneously. The user must provide antialias filtering and proper line termination externally.
Horizontal Phase-Locked Loop
A phase-locked loop generates PXCK, at twice the pixel rate. The reference signal for the horizontal phase-locked loop is generated by the Direct Digital Synthesizer (DDS). The DDS output is constructed with an internal D/A converter and is output from the TMC2072 via the DDS OUT pin. This signal is passed through an external LC filter and input to the horizontal phase-comparator. The frequency of the DDS output is one ninth of that of PXCK. A 20MHz clock is required to drive the DDS. Preferably, this may be input to the TMC2072 via CMOS levels on the CLK IN pin. Alternately, a 20MHz crystal may be directly connected between CLK IN and CLK OUT with tuning capacitors to activate the internal crystal oscillator circuitry.
Analog Clamp
The front-end analog clamp ensures that the input video falls within the active range of the A/D converter. The digitized composite video output can be clamped to the back porch by a secondary digital clamp.
Automatic Gain Adjustment
To accommodate approximately a 15% range in video signal amplitudes, the TMC2072's on-chip AGC circuit
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PRODUCT SPECIFICATION
TMC2072
If incoming video is lost or disconnected after the TMC2072 has locked to it, PXCK and GRS data will continue, but GVSYNC and every eighth GHSYNC will cease until lock is reestablished. The GRS will report the initial subcarrier frequency set by the Format select bits of the Control Register. The TMC2072 will relock to incoming video within two frames after it is restored.
for receiving and transmitting data over the serial interface. When the serial interface is not active, the logic levels on SCL and SDA are pulled HIGH by external pull-up resistors. Data received or transmitted on the SDA line must be stable for the duration of the positive-going SCL pulse. Data on SDA must change only when SCL is LOW. If SDA changes state while SCL is HIGH, the serial interface interprets that action as a start or stop sequence. There are five components to serial bus operation: * * * * * Start signal Slave address byte Base register address byte Data byte to read or write Stop signal
Subcarrier Phase-Locked Loop
A fully-digital phase-locked loop is used to extract the phase and frequency of the incoming color burst. These frequency and phase values are output over the CVBS bus during the horizontal sync period. Fairchild's video decoder and genlockable encoder chips will accept these data directly.
Back Porch Digital Clamp
A digital back-porch clamp is employed to ensure a constant blanking level. It digitally offsets the data from the A/D converter to set the back porch level to precisely 3Ch for NTSC and 40h for PAL. When the digital clamp is enabled, the CVBS video output data is the A/D conversion result minus the back porch level plus 3Ch (40h for PAL). The back-porch level is low-pass filtered to minimize streaking artifacts from subtle line-to-line variations.
When the serial interface is inactive (SCL and SDA are HIGH) communications are initiated by sending a start signal. The start signal is a HIGH-to-LOW transition on SDA while SCL is HIGH. This signal alerts all slaved devices that a data transfer sequence is coming. The first eight bits of data transferred after a start signal comprise a seven bit slave address and a single R/W bit. The R/W bit indicates the direction of data transfer, read from or write to the slave device. If the transmitted slave address matches the address of the device (set by the state of the SA2:0 input pins.), the TMC2072 acknowledges by bringing SDA LOW on the 9th SCL pulse. If the addresses do not match, the TMC2072 does not acknowledge.
Digitized Video Output
The digitized 8-bit video output is provided over an 8-bit wide CVBS data port, synchronous with PXCK and LDV. Subcarrier frequency, subcarrier phase, and Field ID data (GRS) are transmitted in 4-bit nibbles over CVBS3-0 during the horizontal sync tip period at the PXCK rate.
Table 1. Serial Port Addresses
Microprocessor Interface
The TMC2072 is controlled by a standard 2-wire bus. Up to eight TMC2072 devices may be connected to the 2-wire serial interface with each device having a unique address. The 2-wire interface comprises a clock input (SCL) and a bi-directional data (SDA) pin. The TMC2072 acts as a slave
A6 1
A5 0
A4 0
A3 0
A2 A1 A0 (SA2) (SA1) (SA0) 1/0 1/0 1/0
The address is 1000 SA2 SA1 SA0.
tPWLCS SCL tSA SDA tHA
tPWHCS
SA2-SA0 tDOM D7-D0 tDOZ
65-2072-02
tDOM
Figure 1. Microprocessor Parallel Port - Read Timing REV. 1.0.4 6/19/01
3
TMC2072
PRODUCT SPECIFICATION
Data Transfer via Serial Interface
For each byte of data read or written, the MSB is the first bit of the sequence. If the TMC2072 does not acknowledge the master device during a write sequence, the SDA remains HIGH so the master can generate a stop signal. If the master device does not acknowledge the TMC2072 during a read sequence, the TMC2072 interprets this as "end of data." The SDA remains HIGH so the master can generate a stop signal. Writing data to specific control registers of the TMC2072 requires that the 8-bit address of the control register of interest be written after the slave address has been established. This control register address is the base address for subsequent write operations. The base address autoincrements by one for each byte of data written after the data byte intended for the base address. If more bytes are transferred than there are available addresses, the address will not increment and remain at its maximum value of 10h. Any base address higher than 10h will not produce an ACKnowledge signal. If no ACKnowledge is received from the master, the encoder will automatically stop sending data. Data are read from the control registers of the TMC2072 in a similar manner. Reading requires two data transfer operations: The base address must be written with the R/W bit of the slave address byte LOW to set up a sequential read operation. Reading (the R/W bit of the slave address byte HIGH) begins at the previously established base address. The address of the read register autoincrements after each byte is transferred.
To terminate a read/write sequence to the TMC2072, a stop signal must be sent. A stop signal comprises a LOW-toHIGH transition of SDA while SCL is HIGH. A repeated start signal occurs when the master device driving the serial interface generates a start signal without first generating a stop signal to terminate the current communication. This is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines.
Serial Interface Read/Write Examples
Write to one control register Start signal Slave Address byte (R/W bit = LOW) Base Address byte Data byte to base address Stop signal Write to four consecutive control registers Start signal Slave Address byte (R/W bit = LOW) Base Address byte Data byte to base address Data byte to (base address + 1) Data byte to (base address + 2) Data byte to (base address + 3) Stop signal Read from one control register Start signal Slave Address byte (R/W bit = LOW) Base Address byte
SDA tBUFF tSTAH SCL tDAH
65-2072-03
tDHO tDAL
tDSU
tSTASU
tSTOSU
Figure 2. Serial Port Read/Write Timing
SDA STOP START STOP START
SCL
65-2072-04
Figure 3. Serial Interface - Start/Stop Signal
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REV. 1.0.4 6/19/01
PRODUCT SPECIFICATION
TMC2072
Stop signal Start signal Slave Address byte (R/W bit = HIGH) Data byte from base address Stop signal Read from four consecutive control registers Start signal Slave Address byte (R/W bit = LOW) Base Address byte
Stop signal Start signal Slave Address byte (R/W bit = HIGH) Data byte from base address Data byte from (base address + 1) Data byte from (base address + 2) Data byte from (base address + 3) Stop signal
Pin Assignments
80 81 51 50 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name SA0 SA1 SA2 SDA SCL VDD RESET DGND NC NC NC NC NC NC NC DGND INT VDD NC NC CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name VDD DGND CVBS5 CVBS6 CVBS7 BURL GHSYNC GVSYNC VALID FID0 FID1 NC DGND DGND LDV DGND VDD NC VDD PXCK DGND DGND VDD VDDA AGND Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name VDDA VDDA NC NC AGND NC RB VIN3 NC VDDA VIN2 NC AGND VDDA VIN1 NC AGND RT AGND VREF NC AGND VDDA AGND CBYP Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name NC PFD IN NC NC NC AGND DDS OUT NC NC NC PXCK SEL VDDA COMP AGND DGND CLK IN VDD CLK OUT EXT PXCK DGND DGND DGND VDD NC VDD
65-2072-05
100 1 30
31
Note: 1. NC = No internal connection between package and IC. Fairchild Semiconductor recommends leaving these pins open to simplify board upgrades to potential future genlock chips.
Pin Definitions
Pin Name Video Input VIN1-3 Clocks CLK IN 91 CMOS 20 MHz DDS clock input. 20 MHz CMOS clock input to DDS. This pin may also be used along with CLK OUT for directly connecting crystals. Inverted clock output. Inverted DDS clock output. This pin may also be used along with CLK IN for directly connecting a crystal. 2x Pixel clock output. 2x oversampled line-locked clock output. 65, 61, 58 1.23Vp-p Composite Video Input. Video inputs,1.235 Volts peak-to-peak, sync tip to peak color Pin Number Pin Type Function
CLK OUT PXCK
93 45
CMOS CMOS
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5
TMC2072
PRODUCT SPECIFICATION
Pin Definitions (continued)
Pin Name LDV Pin Number 40 Pin Type CMOS Function Pixel clock output. Delayed pixel clock output. LDV runs at 1/2 the rate of PXCK and its rising edge is useful for transferring CVBS digital video from the TMC2072 to the TMC22x9x Digital Video Encoders. External PXCK input. Input for external PXCK clock source. PXCK source select. Select input for internal or external PXCK. When HIGH, the internally generated line-locked PXCK is selected. When LOW, the external PXCK source is enabled. Horizontal sync output. When the TMC2072 is locked to incoming video, the GHSYNC pin provides a negative-going pulse after the falling edge of each horizontal sync pulse. When the device is locked to a stable video signal, there is a fixed number of PXCK clock cycles between adjacent falling edges of GHSYNC. If no video signal is present and LEADLAG is less than 4A(hex), the TMC2072 will output normal, evenly-spaced horizontal pulses. If no video signal is present and LEADLAG exceeds 88(hex), the TMC2072 will omit every eighth Hsync pulse. As LEADLAG is increased from 49h to 89h, seven out of every eight Hsyncs will be unaffected, but the eighth will shrink by one clock cycle per LSB step, until it disappears entirely at 89h. Vertical sync output. When the TMC2072 is locked to incoming video, the GVSYNC pin provides a negative-going edge after the start of the first vertical sync pulse of a vertical blanking interval. If no video signal is present on the selected input pin, GVSYNC will remain continuously at logic high, until a signal is selected and lock is reestablished. A system designer requiring a free-running vertical sync may wish to provide this with an external pixel counter. Composite output bus. 8-bit composite video data are output on this bus at 1/2 the PXCK rate. During horizontal sync, field ID, subcarrier frequency, and subcarrier phase are available on this bus. Odd/even ("top/bottom") field flag. LOW denotes the first field of a video frame; HIGH, the second. Bruch blanking flag. In PAL, LOW denotes a frame with burst blanked on line 310, whereas HIGH denotes burst detected on line 310. FID[1] is valid only in PAL and only when FID[0] is high and should be interpreted as follows: FID[1:0] 01 11 P l/O SA[2:0] SDA SCL 3-1 4 5 R-bus R-bus R-bus chip address, 3 LSBs. Full 7-bit address = {1, 0, 0, 0, SA[2], SA[1], SA[0]} R-bus bidirectional data line. R-bus clock line (input/slave only) PAL Field Number II or VI IV or VIII
EXT PXCK PXCK SEL
94 86
CMOS CMOS
Digital Video GHSYNC 32 CMOS
GVSYNC
33
CMOS
CVBS7-0
30-28, 25-21
CMOS
FID[0] FID[1]
35 36
CMOS CMOS
6
REV. 1.0.4 6/19/01
PRODUCT SPECIFICATION
TMC2072
Pin Definitions (continued)
Pin Name RESET Pin Number 7 Pin Type TTL Function Master reset input. Bringing RESET LOW forces the internal state machines to their starting states, loads the Control Register with default values, and disables outputs. Bringing RESET HIGH restarts the TMC2072 in its default mode. Interrupt output. This output is LOW if the internal horizontal phase lock loop is unlocked with respect to incoming video for 128 or more lines per field. After lock is established, INT goes HIGH. HSYNC locked flag. Hsync locked flag. When high, this output indicates that the most recent incoming horizontal sync has been detected within 16 pixels of its expected position. It goes low if no sync is encountered during this 16-pixel window, as during a typical VCR headswitch line. Once the chip has locked to a clean video source, this flag should remain high continuously. If the chip has locked to a VCR, this flag will typically go low for one (or sometimes two) lines at the bottom of each field. Burst lock flag. When high, this output indicates that the chip's internal subcarrier synthesizer is phase-aligned with the current line's incoming chroma burst. The flag goes low when the internal and external phases diverge. VREF input/output. +1.23 Volt reference. When the internal voltage reference is used, this pin should be decoupled to AGND with a 0.1 F capacitor. An external +1.2 Volt reference may be connected here, overriding the internal reference source. Compensation capacitor. Compensation for DDS D/A converter circuitry. This pin should be decoupled to VDDA with a 0.1 F capacitor. A/D VREF decoupling. Decoupling points for A/D converter voltage references. These pins should be decoupled to AGND with a 0.1 F capacitor. Internal DDS output. Analog output from the internal Direct Digital Synthesizer D/A converter, at 1/9 the PXCK frequency. Horizontal PLL input. Analog input to the Phase/Frequency Detector of the horizontal phase-locked loop. 1 F Comparator bypass. Decoupling point for the internal comparator reference of the Phase/Frequency Detector. This pin should be decoupled to AGND with a 0.1 F capacitor. Analog power supply. Positive power supply to analog section. All pins must be connected. Digital power supply. Positive power supply to digital section. All pins must be connected. Analog ground. Ground for analog section. All pins must be connected. Digital ground. Ground for digital section. All pins must be connected.
INT
17
TTL
VALID
34
TTL
BURL
31
TTL/ CMOS
Analog Interface VREF 70 +1.23 V
COMP
88
0.1 F
RB, RT
57, 68
0.1 F
PLL Filter DDS OUT PFD IN CBYP 82 77 75
Power Supply VDDA VDD Ground AGND DGND 50, 55, 63, 67, 69, 72, 74, 81, 89 8, 16, 27, 38, 39, 41, 46, 47, 90, 95-97 0.0 V 0.0 V 49, 51, 52, 60, 64, 73, 87 6, 18, 26, 42, 44, 48, 92, 98, 100 +5 V +5 V
REV. 1.0.4 6/19/01
7
TMC2072
PRODUCT SPECIFICATION
Control and Status Register Bit Functions
Summary
Register Reg 00 Reg 01 Reg 02 Reg 03 Reg 04 Reg 05 Reg 06 Reg 07 Reg 08 Reg 09 Reg 0A Reg 0B Reg 0C Reg 0D Reg 0E Reg 0F Function 97h (year of revision) 20h (part #) 72h (part #) 01h (silicon revision #) Reserved Lock flags; sync tip Blank level Reserved Format; clock rate; freerun; clamp; reset HSync lead/lag Gain; loop filter bandwidth; subpixel sync & clk position Video source select Vsync delay Sync tip set Output timing, tristate Reserved read only read only read only read only read only read only
Details
Bit Name Function Read Only Read Only Read Only Read Only Read Only Reg 00 97h (year of revision) Reg 01 20h (part #) Reg 02 72h (part #) Reg 03 01h (silicon revision #) Reg 04 Reserved Reg 05 Lock Flags & Sync Height 7 BURST_DET Each time a high-frequency signal is detected during a video line's normal expected burst interval, this flag goes high until the next line's expected burst period. If no high-frequency signal is present during the expected burst interval, this flag goes low. With a standard color television signal input, this flag will be low during vertical field groups and, in PAL, Bruch-blanked lines. [TMC22071A bit 47.] If the subcarrier loop is unlocked on the current video line, i.e., the subcarrier phase error measured during burst exceeds the lock threshold, this flag goes low until the next burst interval. If the phase error is less than the threshold, the flag is reset high. This flag is meaningful only if HLOCK is low. During each video field, if most horizontal sync pulses arrive more than 15 pixels before or after their expected positions, this flag will go high. If most of the field's incoming horizontal syncs fall within 15 pixels of their expected positions, this flag will go low. [TMC22071A bit 56.] These bits report the each line's average sync tip level out of the A/D converter (as observed over CVBS). For a clean signal, the reported value will match the sync tip set in Reg 0D, below.
6
BURST LOCK
5
HLOCK
4:0
ST
8
REV. 1.0.4 6/19/01
PRODUCT SPECIFICATION
TMC2072
Details (continued)
Bit 7:0 Name BP Function Read Only Blank level, as measured at the low-pass-filtered A/D output during each line's color back porch. For a standard video input, its decimal value will be approximately 60 (NTSC) or 64 (PAL). [TMC22071A bits 55:48.] Reg 06 Blank level
Reg 07 Reserved Reg 08 Standard and Clock Rate Select 7:6 V_STD Video Standard. These two control bits select the incoming video standard, viz: 00 NTSC, NTSC-EIAJ (power-on default) 01 PALM (Brazil) 10 PALB,G,H,I 11 PALN (Argentina) [With bits 5:4, these bits cover all functions of TMC22071A bits 3:1.] 5:4 CK_RATE Pixel Clock/Sample Rate. Pixel (sample) rate selector, as follows: 00 12.27 MHz (power-on default; 525-line VGA) 01 13.5 MHz (D1 television rate) 10 14.75 MHz (625-line square-pixel VGA) TMC2072-1 only 11 15.0 MHz TMC2072-1 only Note: The 12.27 MHz pixel rate is reserved for 525-line television standards (NTSC, PAL-M), whereas the 14.75 and 15.0 MHz rates are for 625-line standards (all other PAL) only. Bit combinations 0x1x and 1x00 may yield stable composite data samples, sync pulses, and pixel clock, but no useful color subcarrier information. 3 FREERUN Freerun vs. Genlock Operation. LOW (power-on default): Standard genlock mode, in which the PXCK, GHSYNC, and GVSYNC lock to the incoming video's observed sync pattern. HIGH: GHSYNC is counted down from a free-running PXCK, which is unrelated to the incoming video. [TMC22071A bit 26.] Genlock Reference Signal Enable. LOW (power-on default): Loop-predicted subcarrier phase and frequency data (GRS) are sent over CVBS during each horizontal sync pulse. HIGH: GRS data suppressed, such that the CVBS datastream is just the digitized incoming video signal. [TMC22071A bit 33.] HIGH (power-on default): vertically low-pass filtered digital porch clamp enabled. LOW: digital clamp disabled [TMC22071A bit 34, except that the TMC22071A clamp has no vertical filter.] Master Software Reset Control. HIGH (power-on default & self-reset state): normal operation. LOW: Bringing this "one-shot" control low resets all internal state machines and registers except the microprocessor control bits themselves. The bit then sets itself high, permitting normal operation. (Because it automatically returns to the high state, this bit will always appear as a 1 when read through the microprocessor port.) [TMC22071A bit 0.] Hsync Lead/lag Control (in one-pixel = two-PXCK increments). Power-on default = 80 Hex. To advance (delay) GHSYNC and GVSYNC relative to the video input, decrease (increase) the value. Program code 79h, with sub pixel control = 0.5 will align the GHSYNC output with the falling sync edge of the input video. [TMC22071A bits 24:17.]
2
BPFOUT
1
DC_CLAMP
0
S_RESET
Reg 09 Lead-Lag 7:0 LEAD_LAG
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TMC2072
PRODUCT SPECIFICATION
Details (continued)
Bit 7 Name V_GAIN Function Analog Gain into A/D Converter. LOW (power-on default): unity gain, suitable for nominal 1-volt (sync tip to reference white) video signals. HIGH: 1.5 X gain, for over-terminated video signals with approximately 200mV sync tips. [TMC22071A bit 9.] Reserved, test bit for DDSDAC; reset low (power-on default) Horizontal Phase-Locked Loop Filter Bandwidth. LOW (power-on default): narrow H loop filter to minimize jitter with clean video sources. HIGH: wide filter bandwidth, to better accommodate jittery or noisy sources. Sample Clock (and Sync Signal) Subpixel Offset Timing Control. Format is fractional two's complement, i.e., 0.SFFFF, where bit 4, the signed most significant bit (S), represents 1 PXCK or 1/2 pixel. Thus, the programming range is 01111 = +15/32 pixel to 10000 = -16/32 pixel. A value of 01000 will advance the sample clock and syncs by 1/4 pixel relative to the incoming video, whereas a value of 11000 will retard them the same amount. The power-on default value of 0 nominally aligns the sample clock with the center of the incoming signal's falling sync edges. [TMC22071A bits 16:12.] Reserved, reset low (power-on default) NCOMP SOURCE Reserved, test bit: noise comparator disable; reset low (power-on default) These two bits determine which of the three analog input lines is active, as follows: 00 VIN1 (power-on default) 01 VIN2 1X VIN3. [TMC22071A bits 8:7.] 3 2:0 7 6 FID FREE SCALE ANTEST Reset low (power-on default) to compensate burst PLL for line-by-line changes in sampling rate. Set high to disable compensation (test purpose only). Reserved, analog circuit test bits; reset low (power-on default) Reserved, reset low (power-on default) LOW (power-on default): The color frame identifier (FID[1] in NTSC) toggles smoothly, but with no guaranteed relationship to the incoming color burst phase. HIGH freezes FID[1] in NTSC mode, if a two-field (odd/even only) sequence is desired. Reserved, reset low (power-on default) DLYRPTF Delay Field i.d. Update. LOW (power-on default): FID will increment at the start of each incoming vertical sync pulse group. (NTSC lines 4 and 266.) HIGH: FID will increment at the start of the next line after the start each incoming vertical sync. Delay GVSYNC Output. LOW (power-on default): TMC2072 will generate a GVSYNC falling edge as it predicts the start of a new vertical sync series. This is recommended for laser disk or higher quality video signals, for which the chip can easily predict video field timing. HIGH: TMC2072 will generate a GVSYNC falling edge on the line after it detects the start of a vertical sync series. This is recommended for jittery input signals, if a one-line upward image displacement is acceptable. Reg 0A Gain, loop filter, subpixel adjust
6 5
DDS_TEST HFILT
4:0
SUBPIX
Reg 0B Input select 7 6 5:4
Reg 0C Field and Vsync reporting
5:3 2
1
DLYRPT
10
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PRODUCT SPECIFICATION
TMC2072
Details (continued)
Bit 0 Name ENAGC Function Re-Enable Automatic Gain Control. HIGH (self-resetting one-shot): Initiates a new, self-terminating one-frame AGC sequence, independent of sync lock status. LOW (power-on default and self-reset): AGC is enabled for one frame when video sync is initially acquired, and each time sync is lost and reacquired. [TMC22071A bit 25]. Reserved ST[3:0] Programmable Sync Tip Value. Power-on default = 0. Recommended setting = 3. When the chip has achieved stable lock, this will be the average value output over CVBS during sync tips and equalization pulses. [TMC22071A bit 43:40.] LOW (power-on default): Phase of PXCK output matches that of the TMC22071A. HIGH: Phase of PXCK output is inverted, relative to that of the TMC22071A. LOW (power-on default): Phase of LDV output matches that of the TMC22071A. HIGH: Phase of LDV output is inverted, relative to that of the TMC22071A. LOW (power-on default): PXCK output timing matches that of TMC22071A. HIGH: PXCK output is delayed approximately 5-10ns, to simplify interface timing in some systems. LOW (power-on default): LDV output timing matches that of TMC22071A. HIGH: LDV output is delayed approximately 5-10ns, to simplify interface timing in some systems. LOW (power-on default): Digital outputs CVBS0-7, FID(2:0) and GV/GHSYNC are tristated, to avoid bus contentions elsewhere on the system. HIGH: These pins are enabled, for normal operation. LOW (power-on default): If the Hloop loses lock (Hlock\ goes high), the CVBS port will output the default subcarrier frequency and cumulative phase keyed to each GHSYNC falling edge, and the raw output of the A/D converter at all other times. In this case, since the incoming video and internal state machine are asynchronous, GRS data may appear anywhere along each digitized video line. HIGH: If the Hloop loses lock, the CVBS data port will yield only the default subcarrier phase and frequency data, and zero at all other times. Reserved, reset low (power-on default) Reserved, reset low (power-on default)
Reg 0D Sync Tip Set 7:4 3:0
Reg 0E 7 6 5 FLIPPX FLIPLDV XDLY
4
VDLY
3
ENVHCVBS
2
FORCEZERO
1:0 Reg 0F 7:0
REV. 1.0.4 6/19/01
11
TMC2072
PRODUCT SPECIFICATION
Horizontal Timing
Horizontal line rate is determined by the V_STD control bits. Figure 4 illustrates the horizontal blanking interval. Figure 5 completes the definition of timing parameters with vertical blanking interval detail.
2.35 sec PAL 2.3 sec NTSC Equalizing Pulse Video In
H 0.5H 4.7 sec Serration
GVSYNC tVD GHSYNC (Odd Field) GHSYNC (Even Field) tDH
Video In
65-2072-07
Burst
Figure 5. Vertical Sync timing
Programming the TMC2072
tDH GHSYNC
65-2072-06
Figure 4. Horizontal Sync Timing
Upon power-up after bringing RESET LOW, the TMC2072 Control Register is set to default values listed previously. These default values do not necessarily render the TMC2072 operational in any specific application. Before the TMC2072 is expected to acquire input video, its Control Register must be loaded with control values specific to its use.
Table 2. TMC2072 Timing Options
Standard NTSC, PAL-M NTSC-D1 PAL-D1 PAL-VGA* PAL-VGA*
*TMC2072-1 only
Field Rate (Hz) 59.94 59.94 50.00 50.0 50.0
Line Rate (kHz) 15.734264 15.734264 15.625 15.625 15.625
Pixel Rate (Mpps) 12.2727+ 13.50 13.50 14.75 15.0
PXCK Frequency (MHz) 24.54+ 27.0 27.0 29.0 30.0
Plxels Per Line 780 858 864 944 960
Table 3. Control Register Example Data
Register 8 D E Value 10h 03h 08h Function 13.5 MHz Pixel Rate Sync tip = 3 Enable Outputs
Assumptions: Clean 1-volt (sync to ref white) signal on VIN1. All other control registers left in power-up states.
12
REV. 1.0.4 6/19/01
PRODUCT SPECIFICATION
TMC2072
CVBS Bus Data Formats
The CVBS bus outputs a Genlock Reference Signal (GRS) along with the 8-bit digital composite video data. The range of output data versus video input voltage is illustrated in Figure 6 where sync tip and blanking levels are controlled by the digital backporch clamp of the TMC2072. During horizontal sync, the TMC2072 outputs field identification, subcarrier frequency, and subcarrier phase information on the CVBS bus.
Peak Chrominance Peak Luminance PAL-M NTSC PAL FEh D2h FFh CFh
Field identification is output on CVBS2-0. The LSB, CVBS0, will be LOW during odd fields and HIGH for even fields. When NTSC operation is selected, CVBS1-0 count 00,01,10,11 for fields 1 through 4 respectively. When PAL operation is selected, CVBS2-0 count 000, 001, 010, etc. to 111 for fields 1 through 8, respectively. CVBS3 indicates V-component inversion in PAL. It is HIGH for NTSC lines (burst 135) and LOW for PAL lines (burst 225) Subcarrier frequency is sent out in a 24-bit binary representation in six 4-bit nibbles on CVBS3-0. Subcarrier frequency, f23-0, is that of the on-chip burst PLL. Subcarrier phase, 23-0, is also sent out in a 24-bit binary representation in six 4-bit nibbles on CVBS3-0. Bit 23 is the MSB.
Back Porch Burst Sync Tip Blanking 3Ch 03h 40h 03h
65-2072-08
Figure 6. Output Data vs. Input Video Level
PXCK 0 GHSYNC 1 2 3 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
CVBS3:0
PIXEL
PIXEL
PIXEL
FID
f23:20 f19:16 f15:12 f11:8
f7:4
f3:0
23:20 19:16 15:12 11:8
7:4
3:0
PIXEL
PIXEL
FREQUENCY FIELD IDENTIFICATION
PHASE
65-2072-09
Figure 7. Genlock Reference Signal (GRS) Format
tPWHPX PXCK tDO GHSYNC tXL LDV tHO CVBS7:0
tPWHPX
1/fPXCK
tXV
PIXEL 0
PIXEL 1
65-2072-10
Figure 8. CVBS Bus Video Data Format
REV. 1.0.4 6/19/01
13
TMC2072
PRODUCT SPECIFICATION
SDA / R/W tBUFF tSTAH tDAL SCL/CS tDAH
24469A
tDHO
tDSU
tSTASU
tSTOSU
Figure 9. Serial Port Read/Write Timing
SDA / R/W
MSB
LSB
ACK
SCL/CS
24470A
Figure 10. Serial Interface - Typical Byte Transfer
SDA / R/W
A6
A5
A4
A3
A2
SA1
SA0
R/W
ACK
SCL/CS
65-3648-05
Figure 10A. Chip Address with Read/Write Bit
Equivalent Circuits
VDD n Substrate VDD
2k PFD IN CBYP +2.4 V + - p
VDD p
n VDD
p
DDS OUT 150
65-2072-11
65-2072-12
Figure 11. Equivalent PFD IN Circuit
Figure 12. Equivalent DDS OUT Circuit
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REV. 1.0.4 6/19/01
PRODUCT SPECIFICATION
TMC2072
VDD n Substrate p
VDD
p
Input
Output n
n
65-2072-13
65-2072-14
Figure 13. Equivalent Digital Input Circuit
Figure 14. Equivalent Digital Output Circuit
tDOM CS
tHOM
0.5 V
tDOZ
D0
Hi-Z
2.0 V 0.8 V
65-2072-15
0.5 V
Figure 15. Transition Levels for Three-State Measurements
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter Power Supply Voltage Input Voltage Digital Outputs Applied Voltage2 Forced Current Temperature Operating, Case Operating, Junction Lead Soldering (10 seconds) Vapor Phase Soldering (1 minute) Storage -65 -60 130 150 300 220 150 C C C C C
3,4
Min. -0.5 -0.5 -0.5 -6.0
Max. 7.0 VDD + 0.5 VDD + 0.5 6.0 1
Unit V V V mA sec
Short Circuit Duration (single output in HIGH state to GND)
Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range, and measured with respect to GND. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current, flowing into the device. REV. 1.0.4 6/19/01
15
TMC2072
PRODUCT SPECIFICATION
Operating Conditions (for standard temperature range)
Parameter VDD VIH Power Supply Voltage Input Voltage, Logic HIGH TTL Inputs CMOS Inputs VIL Input Voltage, Logic LOW TTL Inputs CMOS Inputs IOH lOL VIN VREF TA tDAL tDAH tSTAH tSTASU tSTOSU tBUFF tDSU tDHO Output Current, Logic HIGH Output Current, Logic LOW Video Input Signal Level, Sync Tip to Peak White External Reference Voltage Ambient Temperature, Still Air SCL Pulse Width, LOW SCL Pulse Width, HIGH SDA Start Hold Time SCL to SDA Setup Time (START) SCL to SDA Setup Time (STOP) SDA Stop to SDA Start Hold Time SDA to SCL Data Setup Time SCL to SDA Hold Time 0 1.3 0.6 0.6 0.6 0.6 1.3 300 300 0.9 1.0 1.235 70 DGND DGND 0.8 1/3 VDD -2.0 4.0 1.1 V V mA mA V V C s s s s ns s ns ns 2.0 2/3VDD VDD VDD V V Min. 4.75 Nom. 5.0 Max. 5.25 Unit V
Serial Microprocessor Interface
Note: 1. Timing reference points are at the 50% level.
Electrical Characteristics (for standard temperature range)
Parameter IDD Power Supply Current1 Conditions Total Current VDD = Max, fPXCK = 30MHz VREF = +1.235V VDD = Max, VIN = 4.0V VDD = Max, VIN = 0.4V IOH = -2.0 mA IOL = 4.0 mA VDD = Max, VIN = VDD VDD = Max, VIN =GND TA = 25C, f = 1 Mhz TA - 25C, f = 1 Mhz TA = 25C, f = 3.58 Mhz 50 4 10 15 2.4 0.4 10 10 15 Min. Typ. 190 Max. 230 Unit mA
IREF IIH IIL VOH VOL IOZH IOZL Cl CO CV RV
Reference Input Current Input Current, Logic HIGH Input Current, Logic LOW Output Voltage, Logic HIGH Output Voltage, Logic LOW Hi-Z Output Leakage current, HIGH Hi-Z Output Leakage current, LOW Digital Input Capacitance Digital Output Capacitance Input Capacitance, VIN1-3 Input Resistance, VIN1-3
100 10 10
A A A V V A A pF pF pF k
Note: 1. Typical IDD with VDD = +5.0 Volts and TA = 25C, Maximum IDD with VDD = +5.25 Volts and TA = 0C.
16
REV. 1.0.4 6/19/01
PRODUCT SPECIFICATION
TMC2072
Switching Characteristics (for standard temperature range)
Parameter tDO tHO fPCK fPXCK tPWHPX tPWHPX tDH tVD tXL tXV Output Delay Time Output Hold Time Pixel Rate Master Clock Rate PXCK Pulse Width, LOW PXCK Pulse Width, HIGH Horizontal Sync to GHSYNC Vertical Sync to GVSYNC PXCK LOW to LDV HIGH PXCK LOW to LDV LOW TMC2072 TMC2072-1 27 MHz 27 MHz For low-jitter video source, Lead - Lag = 80h For low-jitter video source, Lead - Lag = 80h FLIPPX = 0, FLIPLDV = 0 XDLY = 0, VDLY = 0 Conditlons CLOAD = 35 pF Min. 2 3 12 24 12 12 14 14 10 6 Typ. Max. 15 8 15.3 27.4 30.6 Unit ns ns MHz MHz ns ns pxck pxck ns ns
System Performance Characterlstics
Parameter ESCH ESCP tAL VXT Sync time-base variation1 Error1 Subcarrier Phase Min. Typ. Max. 3 2 2 -35 Unit ns degrees frames dB
Line-lock Acquisition Time Channel-to-Channel Crosstalk @3.58 Mhz
Note: 1. NTSC/PAL compliant black burst at nominal input level 10%, frequencies nominal 10 ppm.
+5V Ferrite Bead Digital Supply Plane 10F 0.1F DGND Video A Video B Video C
LPF
6.8 pF 10H 150 pF 390 pF 0.01 F +5V
Analog Supply Plane* 10F 0.1F AGND DDS OUT PFD IN COMP VREF 0.1F 3.3K
VDD VDDA
3.3 F VIN1 75 3.3 F 3.3 F VIN3 75 EXT PXCK RESET SDA SCL SA 2:0 INT VALID VIN2
LPF
75
LPF
TMC2072 Genlocking Video Digitizer
LM385-1.2 RT 0.1F RB CVBS7:0 GHSYNC GVSYNC PXCK LDV 0.1F 8 DIGITAL VIDEO INTERFACE
0.1F
20 MHz, TTL +5V
CLK IN CLK OUT PXCK SEL
CBYP 0.1F
and
must be connected
MICROPROCESSOR INTERFACE
65-2072-16
via low-impedance path
*section of supply plane beneath analog interface circuitry
Figure 16. Typical Interface Circuit
REV. 1.0.4 6/19/01
17
TMC2072
PRODUCT SPECIFICATION
Application Notes
The TMC2072 is a complex mixed-signal VLSI circuit. It produces CMOS digital signals at clock rates of up to 15 MHz while processing analog video inputs with a resolution of less than a few millivolts. To maximize performance it is important to provide an electrically quiet operating environment. The circuit shown in Figure 16 provides an optional external 1.2V reference to the VREF input of the TMC2072. The internal VREF source is adequate for most applications.
Table 4. Crystal Parameters
Parameter Fundamental frequency Tolerance Stability Load Capacitance Shunt Capacitance ESR Value 20 MHz 30 ppm @ 25C 50 ppm, 0C to 70C 20 pF 7 pF Max. 50 , Max.
Flltering
Inexpensive low-pass anti-aliasing filters are shown in Figures 17 and 18. These filters would normally be inserted in the video signal path just before the 75 terminating resistor and AC-coupling capacitor for each of the three video inputs, VIN1-3. The filter of Figure 17 exhibits a 5th-order Chebyshev response with-3dB bandwidth of 6.7MHz and a group delay of 140 nanoseconds at 5MHz. The filter of Figure 18 has been equalized for group delay in the video signal band. Its -3dB passband is 5.5MHz while the group delay is constant at 220 nanoseconds through the DC to 5MHz frequency band.
2.2H 2.2H TMC2072 33 pF CLK IN 20 MHz Crystal 33 pF
65-2072-19
1M 300 CLK OUT
Figure 19. Direct Crystal Connections
Grounding
The TMC2072 has separate analog and digital circuits. To minimize digital crosstalk into the analog signals, the power supplies and ground connections are provided over separate pins (VDD and VDDA are digital and analog power supply pins; DGND and AGND are digital and analog ground pins). In general, the best results are obtained by tying all grounds to a solid, low-impedance ground plane. Power supply pins should be individually decoupled at the pin. Power supply noise isolation should be provided between analog and digital supplies via a ferrite bead inductor on the analog lead. Ultimately all +5 Volt power to the TMC2072 should come from the same power source. Another approach calls for separating analog and digital ground. While some systems may benefit from this strategy, analog and digital grounds must be kept within 0.1V of each other at all times.
470 pF
1000 pF
470 pF
65-2072-17
Figure 17. Simple Anti-aliasing Filter
3.3 H 3.3 H 4.7 H 4.7 H
430 pF
750 pF
430 pF
470 pF 2.2 H
470 pF 910 H
65-2072-18
Unused Video Inputs
The TMC2072's three video inputs (VIN1, VIN2, and VIN3) are high impedance, diode-protected against moderate electrostatic discharge, and DC biased to approximately 1.9V. We recommend tying any unused inputs to ground or to VDD through a 1 M resistor or a capacitor. Unused inputs may also be left open without damaging the part. If grounded directly, a video input port will source less than 1mA when selected.
Figure 18. Group Delay Equalizer Filter
Using a 20 MHz Crystal
In systems where a 20 MHz clock is not available, a crystal may be used to generate the clock to the TMC2072. The crystal must be a 20 MHz "fundamental" type, not overtone. Specific crystal characteristics are listed in Table 4 and the connections are shown in Figure 19.
18
REV. 1.0.4 6/19/01
PRODUCT SPECIFICATION
TMC2072
Interface to the TMC22x5y Decoder
The TMC22x5y Digital Video Decoders have been designed to directly interface to the TMC2072 Digital Video Genlock. The TMC2072 is the source for TMC22x9x input signals CVBS7-0, GHSYNC, GVSYNC, LDV, and PXCK as shown in Figure 20. These signals directly connect to the
TMC22x5y. The serial microprocessor interfaces for TMC22x5y and TMC2072 are identical. The SDA and SCL bus signals from the host microprocessor are shared by the TMC22x5y and TMC2072. Only SA[2:0], VALID, and INT signals are separate from the microprocessor bus.
CVBS7:0 GHSYNC GVSYNC PXCK TMC2072 LDV GENLOCKING VIDEO DIGITIZER RESET SDA
8
CVBS7:0 GHSYNC GVSYNC PXCK LDV
TMC22x5y DIGITAL VIDEO DECODER RESET SDA
SCL
SCL
MICROPROCESSOR INTERFACE
65-2072-20
Figure 20. TMC22x5y Interface Circuit
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Wire-wrap is not an option. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor picture quality. Consider the following suggestions when doing the layout: 1. Keep the critical analog traces (COMP,VREF, RT, RB, DDS OUT, PFD IN, CBYP, and VIN1-3) as short as possible and as far as possible from all digital signals. The TMC2072 should be located near the board edge, close to the analog output connectors. The digital power plane for the TMC2072 should be that which supplies the rest of the digital circuitry. A single power plane should be used for all of the VDD pins. If the analog power supply for the TMC2072 is the same as that of the system's digital circuitry, power to the TMC2072 VDDA pins should be decoupled with ferrite beads and 0.1 F capacitors to reduce noise. The ground plane should be solid, nor cross-hatched. Connections to the ground plane should have very short leads.
4.
Decoupling capacitors should be applied liberally to VDD pins. Remember that not all power supply pins are created equal. They typically supply adjacent circuits on the device, which generate varying amounts of noise. For best results, use 0.1F capacitors in parallel with 10F capacitors. Lead lengths should be minimized. Ceramic chip capacitors are the best choice. If the digital power supply has a dedicated power plane layer, it should not overlap the TMC2072, the voltage reference or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the TMC2072 and its related analog circuitry can degrade performance. CLK should be handled carefully. Jitter and noise on this clock or its ground reference may degrade performance. Terminate the clock line carefully to eliminate overshoot and ringing.
5.
2.
6.
Related Products
* * * * * TMC22x9x Digital Video Encoders TMC2242/TMC2243/TMC2246 Video Filters TMC2081 Digital Video Mixer TMC22x5y Digital Decoders TMC2302 Image Manipulation Sequencer
3.
REV. 1.0.4 6/19/01
19
PRODUCT SPECIFICATION
TMC2072
Mechanical Dimensions
100 Lead MQFP Package - 3.2mm Footprint
Inches Min. A A1 A2 B C D D1 E E1 e L N ND NE
ccc
Symbol
Millimeters Min. Max.
Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Controlling dimension is millimeters. 3. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 4. "L" is the length of terminal for soldering to a substrate. 5. "B" & "C" includes lead finish thickness.
Max.
-- .134 .010 -- .100 .120 .015 .008 .009 .005 .904 .923 .783 .791 .667 .687 .547 .555 .0256 BSC .028 .040 100 30 20 0 -- 7 .004
-- 3.40 .25 -- 2.55 3.05 .38 .22 .23 .13 22.95 23.45 19.90 20.10 16.95 17.45 13.90 14.10 .65 BSC .73 1.03 100 30 20 0 -- 7 .12
3, 5 5
4
D D1 Datum Plane B Pin 1 Indentifier E e 0.076" (1.95mm) Ref Lead Detail E1 .13 (.005) R Min. L .20 (.008) Min. 0 Min. .13 (.30) R .005 (.012) C
See Lead Detail A A2 B A1 Seating Plane Base Plane -CLead Coplanarity ccc C
REV. 1.0.4 6/19/01
20
TMC2072
PRODUCT SPECIFICATION
Ordering Information
Product Number TMC2072KHC Temperature Range TA = 0C to 70C Screening Commercial Package 100-Lead MQFP Package Marking 2072KHC
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com 6/19/01 0.0m 003 Stock#DS30002072 2001 Fairchild Semiconductor Corporation

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